1. Field of the Invention
The present invention relates to a non-volatile memory in which data is electrically rewritable, e.g., a semiconductor storage device such as a flash EEPROM or the like, and to an information device using the non-volatile memory, such as a cellular phone terminal or the like.
2. Description of the Related Art
Conventionally, in a non-volatile semiconductor storage device (a non-volatile memory) in which data is electrically rewritable, e.g., a flash EEPROM, a data read operation is performed as follows: as shown in FIG. 8, the same drain voltage is applied to a memory cell RC0 set at a predetermined threshold value, which is called a xe2x80x9creference cellxe2x80x9d, and to a memory cell MC0 of a memory array on which a data read operation is performed, while the same gate voltage is applied by a reference word line decoder and a normal word line decoder, and a difference between the values of currents flowing through the memory cells RC0 and MC0 is amplified by a sense amplifier S/A, and the result of the amplification is read out as stored data.
In a conventional method for applying a gate voltage to a reference cell RC0, a gate voltage is constantly applied to the reference cell RC0 while the supply voltage is supplied to the storage device (see FIGS. 9 through 11). In another conventional method, a gate voltage is applied to the reference cell RC0 according to an ATD signal which is activated during the data read operation (see FIGS. 12 through 14). Each of these methods will be specifically described below.
FIG. 9 is a block diagram showing an exemplary structure of a primary part of a conventional non-volatile semiconductor storage device 10. FIG. 9 illustrates a method wherein a voltage is constantly applied to each of the word lines of reference cells RC0, RC1 and RC2 while the supply voltage is supplied to the storage device.
In FIG. 9, the conventional non-volatile semiconductor storage device 10 includes: a memory cell array RA formed by a plurality of reference cells RC0-RC2 (hereinafter, referred to as xe2x80x9creference array RAxe2x80x9d): level shifters LS0 and LS1, which form a word line control circuit for controlling the word lines of the reference cells; a memory cell array MA (hereinafter, referred to as xe2x80x9cmemory array MAxe2x80x9d), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPRDEC; and a redundant word line decoder XRDEC.
The reference array RA includes: the reference cell RC0 used in a data read operation; the reference cell RC1 used for verifying deletion of data; and the reference cell RC2 used for verification in a data write operation. A reference cell word line RWL0 is connected to the gates of the reference cells RC0 and RC1, and a reference cell word line RWL1 is connected to the gate of the reference cell RC2. A bit line RBL0 is connected to the drain of the reference cell RC0; a bit line RBL1 is connected to the drain of the reference cell RC1; and a bit line RBL2 is connected to the drain of the reference cell RC2. The sources of the reference cells RC0-RC2 are all connected to a common source line RHS.
The level shifters LS0 and LS1 are powered by a node voltage HWL for word lines. The level shifter LS0 receives a reference cell selection signal SEL0, and outputs a voltage based on the received reference cell selection signal SEL0 to the reference cell word line RWL0, thereby selecting the word line RWL0. The level shifter LS1 receives a reference cell selection signal SEL1, and outputs a voltage based on the received reference cell selection signal SEL1 to the reference cell word line RWL1, thereby selecting the word line RWL1. The reference cell selection signals SEL0 and SEL1 are exclusively activated, such that one of the signals SEL0 and SEL1 is ON (e.g., when the supply voltage VCC is supplied to the storage device 10) while the other is OFF. For example, when the reference cell selection signal SEL0 is ON, the potential of the reference cell word line RWL0 rises, whereby the reference cell word line RWL0 is selected. When the reference cell selection signal SEL1 is ON, the potential of the reference cell word line RWL1 rises, whereby the reference cell word line RWL1 is selected.
The memory array MA includes a plurality of memory cells as memory elements arranged in a matrix along row and column directions. Herein, the description is simplified by referring only to memory cells MC0 and MC1 of the memory array MA. A memory array normal word line MWL is connected to the gate of the memory cell MC0, and a memory array redundant word line ReWL is connected to the gate of the memory cell MC1. A common bit line MBL is connected to each of the drains of the memory cells MC0 and MC1, and a source line MHS is connected to each of the sources of the memory cells MC0 and MC1. The source lines RHS and MHS are generally kept at the ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source lines RHS and MHS are at a high voltage level.
A redundancy determination signal MD, an address signal ADD and a word line enabling ATD signal SPW are input to the normal word line predecoder XPDEC. Based on these signals, the normal word line predecoder XPDEC outputs a normal word line selection signal SX to the normal word line decoder XDEC.
The normal word line decoder XDEC is powered by the node voltage HWL for word lines. Further, the normal word line decoder XDEC receives a normal word line selection signal SX which is output from the normal word line predecoder XPDEC, and outputs a voltage to a predetermined memory array normal word line MWL according to the normal word line selection signal SX, thereby selecting the predetermined memory array normal word line MWL.
The redundant word line predecoder XPRDEC receives the address signal ADD, the word line enabling ATD signal SPW, and a redundant word line address signal BADD. According to these signals, the redundant word line predecoder XPRDEC outputs a redundancy determination signal MD to the normal word line predecoder XPDEC, and a redundant word line selection signal RX to the redundant word line decoder XRDEC.
The redundant word line decoder XRDEC is powered by the node voltage HWL for word lines. Further, the redundant word line decoder XRDEC receives a redundant word line selection signal RX which is output from the redundant word line predecoder XPRDEC, and outputs a voltage to a predetermined memory array redundant word line ReWL according to the redundant word line selection signal RX, thereby selecting the predetermined memory array redundant word line ReWL.
A word line selection operation is now described with reference to the timing chart of FIG. 10, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a non-redundant memory array normal word line is selected.
FIG. 10 shows, from the top to the bottom of FIG. 10, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is a control signal for activating the storage device 10; an output enabling signal OE# which is a control signal for permitting data output; the word line enable ATD signal SPW which is output from an address transition detection circuit (not shown); the potential of the reference cell word line RWL0; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL. When both the chip enabling signal CE# and the output enabling signal OE# are at the ground level, a data read operation can be performed. The chip enabling signal CE# and the output enabling signal OE# are control signals generally employed in a semiconductor memory, and therefore are omitted from the block diagram of FIG. 9.
In a memory in which data is electrically rewritable, e.g., the non-volatile semiconductor storage device 10 (such as a flash EEPROM), data can be read out unless a data write command or data deletion command is issued immediately after the supply voltage is started to be applied. That is, the chip enabling signal CE# for activating the semiconductor chip and the output enabling signal OE# for permitting data output from an output pad are decreased to the ground level, whereby information stored in the memory cell MC0 can be read out.
Referring to FIG. 10, after the storage device 10 is powered on at time t0, the supply voltage VCC begins to rise. Thereafter, at time t1, the node voltage HWL for word lines, which is used for reading of data, begins to rise.
At this time, for the reference cell RC0, the reference cell selection signal SEL0 is ON while the reference cell selection signal SEL1 is OFF (ground level), the word line RWL0 of the reference cell RC0 is charged through the level shifter LS0 with the node voltage HWL for word lines (about DC 5 V). Furthermore, the bit line RBL0 is selected, and the common source line RHS of the reference cell RC0 is controlled so as to be at the ground level. This voltage-controlled state occurs when a read command is issued.
At time t2 which occurs immediately after the storage device 10 is powered on with supply voltage VCC, the storage device 10 is in a data readable state. That is, in this state, data can be read out from the storage device 10 by decreasing the chip enabling signal CE# and the output enabling signal OE# to the ground level.
Then, at time t3, the word line enable ATD signal SPW rises in response to the chip enabling signal CE# reaching the ground level. At time t4, the normal word line selection signal SX rises to the supply voltage level.
At time t5, the potential of the predetermined memory array normal word line MWL rises in response to the rising of the normal word line selection signal SX. Note that since the memory array redundant word line ReWL is not selected in this example, the potential of the memory array redundant word line ReWL remains at the ground level.
After a while, reading of data is completed, and the word line enable ATD signal SPW falls to the ground level at time t6. Accordingly, the potential of the predetermined memory array normal word line MWL falls to the ground level at time t7. During the above operations, the reference cell word line RWL0 of the reference cell RC0 always remains high.
Next, a word line selection operation is described with reference to the timing chart of FIG. 11, which is performed by a word line control circuit for reference cells, a normal word line control circuit for memory array, and a redundant word line control circuit for memory array when a redundant word line is selected. In FIG. 11, a redundancy determination signal MD and a redundant word line selection signal RX are considered in addition to the various signals described above, and a redundant word line is considered in place of the memory array normal word line MWL. The operation from time to through time t3 is totally the same as that described in FIG. 10, and therefore, the description thereof is herein omitted. The following description of the word line selection operation begins with time t4.
As shown in FIG. 11, after a while since the word line enable ATD signal SPW has risen, the normal word line selection signal SX rises to the supply voltage level at time t4, and accordingly, the potential of the memory array normal word line MWL begins to rise. However, immediately after that, a redundancy determination signal MD is issued, and the normal word line predecoder XPDEC receives the redundancy determination signal MD and lowers the normal word line selection signal SX back to the ground level. The normal word line decoder XDEC receives the lowered normal word line selection signal SX and lowers the potential of the memory array normal word line MWL back to the ground level.
Substantially at the same time as the potential of the memory array normal word line MWL being lowered back to the ground level (at time t5), the redundant word line selection signal RX output from the redundant word line predecoder XPRDEC reaches the supply voltage level. As a result, the potential of the memory array redundant word line ReWL rises in substitution for the memory array normal word line MWL.
In this example, the memory array normal word line MWL is switched to the memory array redundant word line ReWL after the potential of the memory array normal word line MWL begins to rise. This is because the normal word line predecoder XPDEC undesirably issues the normal word line selection signal SX while-the redundant word line predecoder XPRDEC is considering whether the word lines should be switched, and accordingly, a certain length of time is required for canceling the normal word line selection signal SX by the redundancy determination signal MD.
After reading of data is completed, the word line enable ATD signal SPW falls to a low level (GND level) at time t6. Accordingly, the redundant word line selection signal RX falls at time t7, and as a result, the potential of the memory array redundant word line ReWL falls to the ground level.
FIG. 9 shows also the reference cell RC1 used for verifying deletion of data and the reference cell RC2 used for verification in a data write operation. These cells are now briefly described below.
When a data write operation in the memory array MA is performed, a verifying operation is performed for determining whether or not writing of data is normally performed. During the verifying operation, the reference cell selection signal SEL1 is ON (high level) whereas the reference cell selection signal SEL0 is OFF (low level). Meanwhile, the bit line RBL2 is selected so that the bit line RBL0 of the reference cell RC0 for reading data is unselected. As a result, the reference cell RC2 becomes accessible. On the other hand, the common source line RHS is at the ground level, and the node voltage HWL for word lines is increased to, e.g., about 6 V, so as to perform a verifying operation.
In the case where a delete operation is performed on the memory array MA, a verifying operation is performed for determining whether or not the deletion operation has been normally completed. In this case, the reference cell selection signal SEL0 is ON (high level) whereas the reference cell selection signal SEL1 is OFF (low level). As a result, the bit line RBL1 is selected so that the reference cell RC1 for verifying deletion of data becomes accessible. On the other hand, the common source line RHS is at the ground level as in the write verifying operation, and the node voltage HWL for word lines is increased to, e.g., about 5 V, so as to perform a verifying operation.
FIG. 12 is a block diagram showing another exemplary structure of a primary part of a conventional non-volatile semiconductor storage device 11. FIG. 12 illustrates a method wherein a voltage is applied to a reference cell word line RWL of a reference cell RC according to the word line enable ATD signal SPW which is activated during a data read operation.
In FIG. 12, the conventional non-volatile semiconductor storage device 11 includes: a memory cell array RA including a reference cell RC (hereinafter, referred to as xe2x80x9creference array RAxe2x80x9d); a reference word line control circuit CU; a memory cell array MA (hereinafter, referred to as xe2x80x9cmemory array MAxe2x80x9d), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPRDEC; and a redundant word line decoder XRDEC. The arrangement of the memory array normal word line MWL, a circuit system for selectively controlling the memory array redundant word line ReWL, and the circuit structure of the memory array MA, and operations thereof, are the same as those in the non-volatile semiconductor storage device 10 shown in FIG. 9, and therefore, descriptions thereof are herein omitted.
The reference array RA includes the reference cell RC used for reading data. A reference cell word line RWL is connected to the gate of the reference cell RC; a bit line RBL is connected to the drain of the reference cell RC; and a source line RHS is connected to the source of the reference cell RC. The source line RHS is generally kept at the ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source line RHS is at a high voltage level. Herein, although only the reference cell RC for reading data is shown in FIG. 12, reference cells used for writing of data or a deletion verifying processing may be provided in other reference arrays, or may be provided in the reference array RA of FIG. 12 together with other reference word lines or the like. Herein, the description is focused on the reference cell RC for reading data, and descriptions about the reference cells used for writing of data or in a deletion verifying processing, and interconnections for controlling these reference cells and control circuits used therewith, are omitted.
The reference word line control circuit CU is powered with the node voltage HWL for word lines. The reference word line control circuit CU controls the potential of the reference cell word line RWL. The reference word line control circuit CU receives the word line enable ATD signal SPW which is issued when data is read out and a test word line selection signal SD for selectively controlling the reference cell word line RWL in a forcible manner during the test mode. The reference word line control circuit CU outputs a voltage to a predetermined reference cell word line RWL based on the above signals, thereby selecting the predetermined reference cell word line RWL.
Now, a word line selection operation is described with reference to the timing chart of FIG. 13, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a non-redundant normal word line is selected.
As in FIG. 10, FIG. 13 shows, from the top to the bottom of FIG. 13, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is an input control signal for enabling a read or write operation in the storage device 10 (the storage device 10 can be operated when the chip enabling signal CE# is at the ground level); an output enabling signal OE# (data can be read out when the output enabling signal OE# is at the ground level); the word line enable ATD signal SPW; the potential of the reference cell word line RWL; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL.
Referring to FIG. 13, after the storage device 11 is powered on at time t0, the supply voltage VCC begins to rise. Thereafter, at time t1, the node voltage HWL for word lines, which is used for reading of data, begins to rise.
At time t2, the non-volatile semiconductor storage device 11 (e.g., flash EEPROM or the like) is in a data readable state immediately after it is powered ON. That is, in this state, a data read operation can be carried out by decreasing the chip enabling signal CE# to the ground level.
Then, at time t3, the word line enable ATD signal SPW rises in response to the falling of the chip enabling signal CE#. In response to the rising of the word line enable ATD signal SPW, the reference cell word line RWL is charged with the node voltage HWL for word lines at time t4, and at the same time, the normal word line predecoder XPDEC issues the normal word line selection signal SX.
At time t5, the normal word line predecoder XDEC raises the potential of the memory array normal word line MWL according to an output of the normal word line selection signal SX. Note that the potential of the memory array normal word line MWL rises with a slight delay behind the rising of the reference cell word line RWL due to a decoding operation.
After a while, reading of data is completed, and the word line enable ATD signal SPW falls to the ground level at time t6. Accordingly, the reference cell word line RWL and the memory array normal word line MWL fall to the ground level at time t7.
Next, a word line selection operation is described with reference to the timing chart of FIG. 14, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a redundant word line is selected. In FIG. 14, a redundancy determination signal MD and a redundant word line selection signal RX are considered in addition to the various signals described above, and a redundant word line is considered in place of the memory array normal word line MWL. The operation from time t0 through time t3 is totally the same as that described in FIG. 13, and therefore, the description thereof is herein omitted. The following description of the word line selection operation begins with time t4.
As shown in FIG. 13, after a while since the word line enable ATD signal SPW has risen, the normal word line selection signal SX rises to the supply voltage level at time t4, and accordingly, the potential of the memory array normal word line MWL begins to rise. However, immediately after that, a redundancy determination signal MD is issued, and the normal word line selection signal SX decreases back to the ground level in response to the redundancy determination signal MD at time t5. Further, in response to the decrease of the normal word line selection signal SX to the ground level, the potential of the memory array normal word line MWL decreases back to the ground level.
Substantially at the same time as the decrease in the potential of the memory array normal word line MWL to the ground level (at time t5), the redundant word line selection signal RX rises to the supply voltage level. As a result, the potential of the memory array redundant word line ReWL rises in substitution for the memory array normal word line MWL. The reason why the memory array normal word line MWL slightly pulses between time t4 and time t5 is the same as that described in connection with the example illustrated in FIG. 11.
After reading of data is completed, the word line enable ATD signal SPW falls to a low level at time t6. Accordingly, the redundant word line selection signal RX and the potential of the reference cell word line RWL fall to the ground level at time t7, and as a result, the potential of the memory array redundant word line ReWL falls to the ground level.
The trend in the field of semiconductor storage devices in recent years indicates that the supply voltage level applied to a semiconductor storage device has been decreasing. However, on the other hand, an increase in the speed of reading of stored information from a memory cell has been demanded. For example, in the conventional non-volatile semiconductor storage device 11, reading of stored information (data) from the memory cell can be carried out as follows: the same voltage is applied to the reference cell RC and a memory cell MC0 from which data is to be read out, and a difference between the values of currents flowing through the memory cells RC and MC0 is sensed by a sense amplifier S/A, which is formed by a differential amplifier, whereby reading of data is achieved.
In such a case, a risk of erroneous reading of data can be avoided by starting a sensing operation after a word line of a reference array and a word line for a memory array reach a predetermined voltage. However, in many cases, a reduction in read access time cannot be achieved because of the latency required until the word line of the reference array and the word line for the memory array reach a desired voltage. Thus, in almost all of such cases, the sense amplifier S/A is activated so as to begin a sensing operation before both of the above word lines reach a desired voltage, whereby an increase in access speed is achieved.
However, in the conventional art of FIGS. 9 and 12, the potential of the reference cell word line RWL rises prior to the rising of the potential of the memory array normal word line MWL. This causes some problems, which will be described in detail below with reference to FIGS. 15 through 17.
In FIG. 15, the left part shows a reference cell RC of a non-volatile memory such as a flash memory, and the right part shows a memory cell MC of then on-volatile memory. As shown in FIG. 15, agate voltage VgsR, which is applied to the reference cell RC, is equivalent to a voltage output to a reference cell word line RWL0 of FIG. 9, and is also equivalent to a voltage output to a reference cell word line RWL of FIG. 12. A current IdsR flows between a drain and source of the reference cell RC. On the other hand, a gate voltage VgsM, which is applied to the memory cell MC, is equivalent to a voltage output to the memory array normal word line MWL or the memory array redundant word line ReWL of FIGS. 9 and 12. A current IdsM flows between a drain and source of the reference cell MC.
FIG. 16 shows a graph of the voltage levels VgsR and VgsM of the word lines during reading of data from the memory cells RC and MC, where the horizontal axis represents time t, and the vertical axis represents voltage level V. In this graph, t(a) represents the time when a sensing operation starts (hereinafter, xe2x80x9csensing start timexe2x80x9d), and t(b) represents the time when both the voltage level of the reference cell word line RWL of the memory cell RC and the voltage level of the memory array normal word line MWL of the memory cell MC (or the memory array redundant word line ReWL) reach a predetermined voltage level. At sensing start time t(a), the voltage level VgsR of the word line of the reference cell RC is at the predetermined voltage level in either of the examples of FIGS. 9 and 12.
Part (a) of FIG. 17 shows the relationships between the gate voltages Vgs applied to the gate electrodes of the reference cell RC and the memory cell MC (horizontal axis) and the currents Ids which flow between the source and drain of the cells RC and MC (vertical axis), respectively, at time t(a) of FIG. 16, i.e., before the potential of the memory array normal word line MWL or the memory array redundant word line ReWL which was set in FIG. 16 reaches the predetermined voltage.
Part (b) of FIG. 17 shows the relationships between the gate voltages Vgs (horizontal axis) and the currents Ids which flow between the source and drain of the cells RC and MC (vertical axis), respectively, at time t(b) of FIG. 16, i.e., after the potential of the memory array normal word line MWL or the memory array redundant word line ReWL which was set in FIG. 16 has reached the predetermined voltage.
In the case where the amount of a current flowing through the memory cell MC, from which data is read out, is larger than that flowing through the reference cell RC, i.e., in the case where the threshold of the memory cell MC is lower than that of the reference cell RC, reading of data from the memory cell MC is adversely affected. This case is described below.
Immediately after the sensing start time t(a) shown in FIG. 16, the voltage VgsR of the reference cell word line RWL which is applied to the reference cell RC is generally at the predetermined voltage. However, on the other hand, the gate voltage VgsM of the memory array normal word line MWL (or the memory array redundant word line ReWL) applied to the gate of the memory cell MC, from which data is to be read, is lower than the word line voltage VgsR applied to the reference cell RC (t(a); VgsR greater than VgsM). In this case, the difference xcex94Ids(a) between the current IdsR flowing through the reference cell RC and the current IdsM flowing through the memory cell MC becomes as small as possible as shown in part (a) of FIG. 17. Thus, there is a possibility that the difference cannot be correctly sensed by the sense amplifier S/A so that the storage device results in an erroneous operation, e.g., unintended data is read out.
On the other hand, at time t(b) shown in FIG. 16, both the word line voltage VgsR applied to the gate of the reference cell RC and the word line voltage VgsM applied to the gate of the memory cell MC, from which data is to be read, are at the same predetermined voltage (t(b); VgsR=VgsM). In this case, the difference xcex94Ids(b) between the current IdsR flowing through the reference cell RC and the current IdsM flowing through the memory cell MC is sufficiently large so that it can be correctly sensed by the sense amplifier S/A. As a result, intended data can be read out without causing an erroneous operation.
However, if unintended data is once output immediately after the sensing start time (time t(a)), in many cases, extra time is consumed until intended data is successfully output. This extra time is considerably long especially when a redundant word line is selected, because as described above, a certain length of time is required for switching from a normal word line to the redundant word line.
According to one aspect of the present invention, a semiconductor storage device includes: a memory array including a plurality of memory cells; a reference array including a plurality of reference cells; a decoder section for selecting a memory cell from the memory cells and a reference cell from the reference cells based on address information; and a comparison/output section for comparing a read voltage level from the memory cell selected by the decoder section and a read voltage level from the reference cell selected by the decoder section so as to output a result of the comparison in the form of data, wherein the decoder section simultaneously outputs a selection signal to a word line of the memory cell and a selection signal to a word line of the reference cell.
In one embodiment of the present invention, the memory array includes one or more memory cells respectively connected to a normal word line, and one or more memory cells respectively connected to a redundant word line; and the reference array includes a first reference cell which is compared with the memory cells connected to the normal word line, and a second reference cell which is compared with the memory cells connected to the redundant word line.
In another embodiment of the present invention, when the normal word line is selected, the decoder section selects a first word line connected to the first reference cell simultaneously with selection of the normal-word line; and when the redundant word line is selected, the decoder section selects a second word line connected to the second reference cell simultaneously with selection of the redundant word line.
In still another embodiment of the present invention, the decoder section includes: a selection determination section for determining which of the normal word line and the redundant word line is to be selected based on address information; a normal word line control section for selecting the normal word line according to the address information when it is determined that the normal word line is to be selected; a redundant word line control section for selecting the redundant word line according to the address information when it is determined that the redundant word line is to be selected: a first reference word line control section for selecting the first word line when it is determined that the normal word line is to be selected; and a second reference word line control section for selecting the second word line when it is determined that the redundant word line is to be selected.
In still another embodiment of the present invention, when it is determined that the normal word line is to be selected, the first reference word line control section receives a selection signal for the normal word line or a signal indicating that the normal word line is to be selected, and selects the first word line, using as a trigger, the selection signal for the normal word line or the signal indicating that the normal word line is to be selected; and when it is determined that the redundant word line is to be selected, the second reference word line control section receives a selection signal for the redundant word line or a signal indicating that the redundant word line is to be selected, and selects the second word line, using as a trigger, the selection signal for the redundant word line or the signal indicating that the redundant word line is to be selected.
In still another embodiment of the present invention, a first test signal can be input to the first reference word line control section, and the first reference cell is enforcedly selected in response to the first test signal; and a second test signal can be input to the second reference word line control section, and the second reference cell is enforcedly selected in response to the second test signal.
In still another embodiment of the present invention, an address transition detection signal, which is output in response to detection of a change in the address information, can be input to both the first reference word line control section and the second reference word line control section; and when the address transition detection signal is input, control of reference word lines can be performed.
In still another embodiment of the present invention, the first reference cell and the second reference cell are set to the same threshold value.
In still another embodiment of the present invention, the first reference cell and the second reference cell are commonly connected to the same bit line.
In still another embodiment of the present invention, the load capacitance of a first word line connected to the first reference cell and the load capacitance of a second word line connected to the second reference cell are equal to the load capacitance of the normal word line and the load capacitance of the redundant word line, respectively. Alternatively, the load capacitances of the first word line, the second word line, the normal word line and the redundant word line may be equal.
According to another aspect of the present invention, there is provided an information apparatus for performing a data read operation using one of the above semiconductor storage devices.
An operation of the above-described structure of the present invention is described below.
In the case of reading data from a desired memory cell, if a normal word line, which is not a redundant word line, is selected, the potential of the word line of a reference array rises simultaneously with and in synchronization with a selection signal for selecting the normal word line of the memory array. Alternatively, if the redundant word line is selected, the potential of the word line of a reference array likewise rises simultaneously with and in synchronization with a selection signal for selecting the redundant word line of the memory array.
Since the potential of the word line of the reference cell and the potential of the word line of the memory cell, from which data is to be read, rise simultaneously in synchronization with each other. Thus, in the case of reading data from the memory cell, it is not necessary to wait for both of the word lines reaching a predetermined voltage level. As a result, a read access time can be further shortened without causing an erroneous operation. Due to such an improvement of the data reading speed, a considerable sensing margin can be secured.
Further, the load capacitances of the first and second word lines of the reference array are identical to those of the normal word line and redundant word line of the memory array, respectively. Thus, the rising edges of the potentials of the word lines occur at the same time, and accordingly, a read access time can be further shortened without causing an erroneous operation.
Furthermore, a semiconductor storage device of the present invention can readily be applied to an information apparatus. Thus, in a data read operation, high-speed data reading can be achieved.
Thus, the invention described herein makes possible the advantages of providing (1) a semiconductor storage device wherein a read access time can be shortened without causing an erroneous operation, and (2) an information apparatus using such a semiconductor storage device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.